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FDU48-018 FDU 2.0 变速驱动器 JNFX48-019 54CE--GA-NNNNAN

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产品标题:FDU48-018 FDU 2.0 变速驱动器 JNFX48-019 54CE--GA-NNNNAN--

型号:    变速驱动器 JNFX48-019 54CE--GA-NNNNAN--  

质保:七天验收期,质保期一年

品牌:  FDU48-018 FDU 

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本应用说明显示了访问MPC500系列的C级API例程的示例

TPU寄存器。这些例程可用于访问ROM功能或存储的功能

在DPTRAM中。Freescale应用说明中显示了此API的使用示例

如表6所示。所有这些函数和定义都包含在mpc500_util中。c和

mpc500_实用程序。h文件。这些都包含在标准Freescale C头文件中

MPC500系列(3.0.3版)。标题文件可在飞思卡尔网站上找到。

1功能概述

MPC555和MPC56x设备包括定时处理器单元(TPU)。TPU

这些设备上包含的实际上是TPU的第三个版本,也称为TPU3

TPU是一个具有自己的内存和程序控制的自主处理器。MPC500

设备控制TPU的启动,并可以通过共享

内存空间(参数RAM)。TPU有16个单独的通道,每个通道都有参数

内存MPC500系列的大多数成员都有2个TPU。本应用说明涵盖

CPU到TPU接口和一些可用于与函数接口的基本C例程

编程到TPU通道中。

TPU可以从内置TPU ROM或外部的SRAM执行

TPU(DPTRAM)。DPTRAM是一个双端口TPU RAM,可由主处理器访问

处理器或最多两个TPU。DPTRAM必须由主处理器加载,但它

一旦在任一TPUMCR中设置了EMU位,主CPU就无法写入或读取。

TPU有两个限制:地址空间有限(总共8K,

由2K库组成),它只能从TPU ROM或DPTRAM运行。这个

TPU不能同时访问ROM和DPTRAM,并且只能执行

从一个或另一个。TPU ROM总共有4K ROM,由两个2K库组成。

MPC555和MPC565上主TPU上的DPTRAM总共有6K个

内存,由三个2K库组成。MPC561和MPC563具有8K的DPTRAM(四个

2K银行)。此外,MPC565还有第三个TPU,它有自己的4K DPTRAM(2

银行)。

MPC500处理器在

TPUMCR寄存器。

TPU指令存储器(DPTRAM或ROM)的每个库都可以有一个条目表

指向存储在内存中的函数,并且每个条目位置都与函数关联

数字功能分配给通道功能选择寄存器中的通道。每个

通道可以分配任何功能。条目表有16个函数的空间

This application note shows examples of C level API routines to access the MPC500-family

TPU registers. These routines can be used to access either ROM functions or functions stored

in the DPTRAM. Examples of the use of this API are shown in the Freescale application notes

shown in Table 6. All of these functions and definitions are included in the mpc500_util.c and

mpc500_util.h files. These are included in the standard Freescale C header files for the

MPC500 family (version 3.0.3). The header files are available on the Freescale web site.

1 Functional Overview

The MPC555 and the MPC56x devices include Timing Processor Units (TPU). The TPU

included on these devices is actually the third version of the TPU, also known as TPU3. The

TPU is an autonomous processor with its own memory and program control. The MPC500

device controls the startup of the TPU and can communicate to the TPU through a shared

memory space (parameter RAM). The TPU has 16 separate channels, each with parameter

RAM. Most of the members of the MPC500 family have 2 TPUs. This application note covers

the CPU to TPU interface and some basic C routines that can be used to interface to functions

programmed into the TPU channels.

The TPU can execute from either a built-in TPU ROM or from SRAM that is external to the

TPU (DPTRAM). The DPTRAM is a Dual Port TPU RAM that can be accessed by the main

processor or by up to two TPUs. The DPTRAM must be loaded by the main processor, but it

cannot be written or read by the main CPU once the EMU bit has been set in either TPUMCR.

The TPU has two limitations: it has a limited amount of address space (a total of 8K,

composed of 2K banks), and it can only run from either the TPU ROM or the DPTRAM. The

TPU cannot access both the ROM and the DPTRAM at the same time, and it can execute only

from one or the other. The TPU ROM has a total of 4K of ROM, composed of two 2K banks.

The DPTRAM on the main TPUs on the MPC555 and the MPC565 has a total of 6K of

memory, composed of three 2K banks. The MPC561 and MPC563 have 8K of DPTRAM (four

2K banks). Additionally, the MPC565 has a third TPU that has it’s own 4K of DPTRAM (2

banks).

The MPC500 processor sets the default TPU instruction memory source and bank in the

TPUMCR register.

Each bank of the TPU instruction memory (DPTRAM or ROM) can have an entry table that

points to functions that are stored in memory and each entry location is associated to a function

number. Functions are assigned to channels in the channel function select register. Each

channel can be assigned any function. The entry table has space for 16 functions that

T

 

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