产品标题：P0960KA ZLAM 用于接口模块 FOXBORO INVENSYS
型号: P0960KA ZLAM 用于接口模块
质保：七天验收期，质保期一年
品牌： FOXBORO INVENSYS
产品图片展示
产品详情资料
在TPUMCR2中设置DTPU，可以将TP15配置为输入禁用引脚
直接从硬件禁用TPU3输出的快速方法。
•为T2CLK增加了过滤器和过渡选项。
-T2CLK引脚可通过T2CG和T2CSL位编程，以选通IMB3 Div8
时钟，以阻止它或直接从引脚为TCR2计数器计时。上的T2CLK输入
MC68332 TPU1模块仅检测上升边缘。MPC500系列上的T2CLK输入
TPU3模块现在检测上升、下降或任何边缘。
•仿真内存现在是双端口RAM（DPTRAM），可由2个TPU3共享。
-MPC555和MPC556具有6K，可在2个TPU3模块之间共享。
-MPC561、MPC562、MPC563和MPC564具有可在2 TPU3之间共享的8K
模块。
-MPC565和MPC566有2个DPTRAM模块。2 TPU3之间共享的6K阵列
模块（A和B），以及用于第三个TPU3模块的4K阵列(
了TPUMCR中的位。要重置TPU1，您必须使用此软件重置MC68332
重置设备TPU3可以独立于MPC500上的所有其他模块进行重置
家族设备，允许TPU3从***循环和其他严重软件中恢复
错误。
•增加主禁用引脚。
-通过在TPUMCR2中设置DTPU，可以将TP15配置为输入禁用引脚
直接从硬件禁用TPU3输出的快速方法。
•为T2CLK增加了过滤器和过渡选项。
-T2CLK引脚可通过T2CG和T2CSL位编程，以选通IMB3 Div8
时钟，以阻止它或直接从引脚为TCR2计数器计时。上的T2CLK输入
MC68332 TPU1模块仅检测上升边缘。MPC500系列上的T2CLK输入
TPU3模块现在检测上升、下降或任何边缘。
•仿真内存现在是双端口RAM（DPTRAM），可由2个TPU3共享。
-MPC555和MPC556具有6K，可在2个TPU3模块之间共享。
-MPC561、MPC562、MPC563和MPC564具有可在2 TPU3之间共享的8K
模块。
-MPC565和MPC566有2个DPTRAM模块。2 TPU3之间共享的6K阵列
模块（A和B），以及用于第三个TPU3模块的4K阵列(
输入是IMB3时钟除以一个值
由EPSCK位设置，范围在2到64之间，增量为2。预分频器将其划分
根据TCR1P的值输入1、2、4或8。
•增加了软复位。
-TPUMCR2中的SOFTRST位
10K，具体取决于从中选择的特定设备
MPC500系列。
。
产品实物图片展示
Product Details
rati family device, allowing the TPU3 to recover from infinite loops and other serious software
errors.
• Added master disable pin.
— TP15 can be configured as an input disable pin by setting DTPU in TPUMCR2. This provides
a quick way to disable the TPU3 outputs directly from hardware.
• Added filter and transition options to T2CLK.
— The T2CLK pin can be programmed via the T2CG and T2CSL bits to gate the IMB3 Div8
clock, to block it or to directly clock the TCR2 counter from the pin. The T2CLK input on the
MC68332 TPU1 module only detects rising edges. The T2CLK input on the MPC500 family
TPU3 module now detects rising, falling or any edge.
• Emulation memory is now dual-port RAM (DPTRAM) and can be shared by 2 TPU3s.
— MPC555 and MPC556 have 6K that can be shared between the 2 TPU3 modules.
— MPC561, MPC562, MPC563 and MPC564 have 8K that can be shared between the 2 TPU3
modules.
— MPC565 and MPC566 have 2 DPTRAM modules. A 6K array shared between 2 TPU3
modules (A and B), and a 4K array for the third TPU3 module (
bit in TPUMCR is also set. To reset the TPU1 you have to reset the MC68332, with this soft
reset facility the TPU3 can be reset independently of all the other modules on the MPC500
family device, allowing the TPU3 to recover from infinite loops and other serious software
errors.
• Added master disable pin.
— TP15 can be configured as an input disable pin by setting DTPU in TPUMCR2. This provides
a quick way to disable the TPU3 outputs directly from hardware.
• Added filter and transition options to T2CLK.
— The T2CLK pin can be programmed via the T2CG and T2CSL bits to gate the IMB3 Div8
clock, to block it or to directly clock the TCR2 counter from the pin. The T2CLK input on the
MC68332 TPU1 module only detects rising edges. The T2CLK input on the MPC500 family
TPU3 module now detects rising, falling or any edge.
• Emulation memory is now dual-port RAM (DPTRAM) and can be shared by 2 TPU3s.
— MPC555 and MPC556 have 6K that can be shared between the 2 TPU3 modules.
— MPC561, MPC562, MPC563 and MPC564 have 8K that can be shared between the 2 TPU3
modules.
— MPC565 and MPC566 have 2 DPTRAM modules. A 6K array shared between 2 TPU3
modules (A and B), and a 4K array for the third TPU3 module (
nc.For More Information On This Product, Go to: Compar***n Between the M68332 TPU1 and the MPC500-Family TPU3• Added programmable digital filters:— These allow the control of the ratio between the IMB3 clock and the minimum detectable
pulses. This is programmed through the FPSCK bits in TPUMCR2.• Increased resolution on TCR1
— The MC68332 TPU1 TCR1 resolution has a maximum of 4 clocks (250ns at 16MHz).— The MPC5xx TPU3 TCR1 resolution has a maximum of 2 clocks (35.7ns at 56MHz).• Added support for IMB3 and the MPC500 family interrupt structure.To move the TPU onto the MPC500 family, support was added to interface to the RCPU.• Added modulus prescaler to TCR1 which has an additional /2 to compensate for high clock
speeds.— On the MC68332 the TCR1 prescaler input is the TPU system clock divided by 4 or 32 via the
PSCK bit. The prescaler divides this input by 1, 2, 4 or 8 depending on the value of TCR1P.
— On the MPC500 family devices the EPSCKE bit determines standard or enhanced prescaler
operation. With EPSCKE = 0 (standard mode) the prescaler works as per the TPU1 prescaler.
— With EPSCKE = 1 (enhanced mode) the prescaler input is the IMB3 clock divided by a value
set by the EPSCK bits, ranging between 2 and 64 in increments of 2. The prescaler divides this
input by 1, 2, 4 or 8 depending on the value of TCR1P.
• Added soft reset.
— The SOFTRST bit in TPUMCR2
K or 10K depending on the specific device chosen from the
MPC500 family.
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