2727-RY1正品
¥999.00
1732E-IB16M12R输入模块
¥999.00
1787-PCABL正品
¥999.00
1745-N1输出模块
¥999.00
1734-IV2输入模块
¥999.00
1788-FFCT输出模块
¥999.00
1746-RT29正品
1746-RT29正品
1746-RT29正品
中间输出指令用于存储RLO的中间值，该值是中间输出指令前的位逻辑操作结果。中间输出指令不能用于结束一个逻辑串，因此，中间输出指令不能放在逻辑串的结尾或分支的结尾处。
例3.1.5
M 0.0的缓存器中存放着I 1.0和I 1.1相与后取反的结果；
M 1.1的缓存器中存放着I 1.2和I 1.3相与后取反的结果；
M 2.2的缓存器中存放着I 1.4的逻辑运算结果；
M 3.3的缓存器中存放上述整个逻辑运算的结果。
例3.1.6
M 0.0的缓存器中存放着I 1.0和I 1.1相与的结果；
M 1.1的缓存器中存放着I 1.0、I 1.1、I 1.2和I 1.3四个输入信号相与后取反的结果；
M 2.2的缓存器中存放着整个逻辑运算的结果。
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