CI871K01 处理器模块具备数据记录功能包括过程控制

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ABB CI871K01 处理器模块

多用途控制： ABB CI871K01 处理器模块通常设计成通用控制器，可用于多种应用，包括过程控制、机器控制、自动化生产线等。高性能处理器：这种模块通常配备高性能的处理器，以实现快速响应和高效率的控制。通信接口：模块通常配备通信接口，用于与其他设备或控制系统进行数据交换。通信接口可以包括以太网、Modbus、Profibus等。可编程性： CI871K01 处理器模块通常具有可编程功能，允许用户根据具体应用需求进行自定义配置和编程。实时监测：这种模块通常支持实时数据监测，以帮助操作员迅速识别和响应问题。报警和通知：处理器模块通常能够生成报警和通知，以提醒操作员在出现异常情况时采取行动。数据记录和报告：一些模块具备数据记录功能，可以记录系统操作数据，并生成报告，以供后续分析和维护。工业标准符合：这些模块通常需要符合工业标准和规定，以确保其在工业环境中的可靠性和耐用性。

CI871K01系统的软件设计根据硬件结构的总体划分，也可以分为两大部分来描述。整个系统的运行如图2所示，FPGA和DSP各自的程序独立运行，通过中断信号完成数据的实时交互。FPGA向DSP方向的指令是通过FPGA发送一个EDMA请求，DSP通过响应EDMA请求，建立EDMA通道，开始从FIFO中进行预处理后数据的读取，DSP向FPGA传输数据时，通过向FPGA发送一个中断信号，让其从FIFO中把压缩后的图像数据读出来。整个系统工作流程可以简单描述如下：系统上电后，首先DSP由flash实现自举，并运行引导程序，之后转入EDMA等待状态，FPGA初始化后等待外部图像采集命令。

CI871K01收到图像采集命令后开始进行图像采集，并对采集到的图像进行预处理，预处理后的图像经过FIFO缓冲，在存储一定量的数据之后，FPGA通过半满信号向DSP发送EDMA请求，等待DSP响应，DSP一旦收到来自FPGA的EDMA请求，立即建立EDMA通道，从FIFO中读取数据到L2存储器，存满一帧图像后DSP开始图像压缩，等待一幅图像压缩完成之后，DSP会向FPGA发送中断信号，FPGA在收到中断信号后开始从 FIFO中读取压缩后的图像数据。一帧数据读完后，判断编码信号是否有效，如果有效则按同样的规则对下一帧图像进行压缩，如果无效则通知DSP结束。

Multipurpose control: ABB CI871K01 processor modules are typically designed as general-purpose controllers and can be used in various applications, including process control, machine control, automated production lines, and more. High performance processors: These modules are typically equipped with high-performance processors to achieve fast response and efficient control. Communication interface: Modules are usually equipped with communication interfaces for data exchange with other devices or control systems. Communication interfaces can include Ethernet, Modbus, Profibus, etc. Programmability: CI871K01 processor modules typically have programmable functionality, allowing users to customize configuration and programming based on specific application requirements. Real time monitoring: This module typically supports real-time data monitoring to help operators quickly identify and respond to problems. Alarm and notification: Processor modules are typically able to generate alarms and notifications to alert operators to take action in the event of abnormal situations. Data recording and reporting: Some modules have data recording functions, which can record system operation data and generate reports for subsequent analysis and maintenance. Industry standard compliance: These modules typically need to comply with industry standards and regulations to ensure their reliability and durability in industrial environments.

The software design of the CI871K01 system can also be described in two major parts based on the overall division of hardware structure. The entire system runs as shown in Figure 2, with FPGA and DSP programs running independently and completing real-time data exchange through interrupt signals. The instruction from FPGA to DSP is to send an EDMA request through FPGA. DSP responds to the EDMA request, establishes an EDMA channel, and starts reading preprocessed data from FIFO. When DSP transmits data to FPGA, it sends an interrupt signal to FPGA to read the compressed image data from FIFO. The entire system workflow can be briefly described as follows: After the system is powered on, the DSP is first booted by flash and the boot program is run. Then, it enters the EDMA waiting state, and after FPGA initialization, it waits for external image acquisition commands.

After receiving the image acquisition command, CI871K01 starts image acquisition and preprocesses the collected images. The preprocessed images are buffered in FIFO and stored in a certain amount of data. The FPGA sends an EDMA request to the DSP through a half full signal, waiting for the DSP to respond. Once the DSP receives an EDMA request from the FPGA, it immediately establishes an EDMA channel, reads data from the FIFO into L2 memory, and after one frame of image is fully stored, the DSP starts image compression, After waiting for an image to be compressed, the DSP will send an interrupt signal to the FPGA, which will start reading the compressed image data from the FIFO after receiving the interrupt signal. After reading a frame of data, determine whether the encoded signal is valid. If it is valid, compress the next frame of image according to the same rules. If it is invalid, notify the DSP to end.

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