产品标题：ICS TRIPLEX T9110PXI模块使用方法教程
型号：ICS TRIPLEX T9110
质保：七天验收期，质保期一年
品牌：ICS TRIPLEX
产品图片展示
产品详情资料：
如第3.3节所述，可以选择16个DAC输出中的任何一个通过测试总线2传递给VMIVME-3100 ADC板，以验证DAC输出。如果VMIVME-3200存在于模拟背板中，则可以选择任何DAC输出通过测试总线1发送到该板进行测试。通常，使用两条测试总线之一的编程顺序如下：也可以在程序控制下更新输出，以路由到***的测试总线。如第5.7节所示，电路板必须事先跳线以适应延迟的DAC更新模式。编程顺序如下：D08当写入高电平时，将DAC输出接合到P3连接器，当写入低电平时，从P3连接器断开DAC输出。通电时，此控制位低。D09程序控制启动转换，当输入高时，生成一个信号，将先前加载的DAC的内容传输到二阶寄存器，并更新模拟输出。D10在测试模式下，将高时钟信道地址位A01至A04写入测试寄存器，以选择16个DAC信道输出之一。与D11、D12和D13结合使用，以确定测试模式。
产品英文详情资料：
described in Section 3.3, any of the 16 DAC outputs may be selected to pass to a VMIVME-3100 ADC Board over Test Bus 2 to verify the DAC outputs. If a VMIVME-3200 is present in the analog backplane, then any DAC output can be selected to go to that board for test purposes over Test Bus 1. Generally, the programming sequence for utilizing one of the two test busses is as follows:An output may be also updated under program control to route to a specified test bus. The board must have previously been jumpered to accommodate the delayed DAC update mode, as shown in Section 5.7. The programming sequence is as follows:D08 When written high, engages DAC outputs to the P3 connector, and disengages DAC outputs from P3 connector when written low. At power-up, this control bit is low. D09 Program Control Start Convert, when input high, generates a signal that transfers contents of previously loaded DACs to the second rank register and updates the analog ouput. D10 In test mode, written high to clock channel address bits A01 through A04 into test register to select one of 16 DAC channel outputs. Used in conjunction with D11, D12 and D13 to determine test modes.
